1. Field of the Invention
The present invention relates generally to the testing of integrated circuit dies. More specifically, but without limitation thereto, the present invention relates to locating manufacturing defects in an integrated circuit die by identifying areas of multiple net failures.
2. Description of Related Art
The combination of logic tests for specific logic paths and computer automated design (CAD) navigation tools that can map nets in an integrated circuit die allows the physical path of a failed net in the die to be displayed and plotted after a performance test. The plots from a number of tests performed on different dies for identical test paths may be combined to produce a stacked map for displaying the locations of the highest number of failures to identify physical features on the die that are most likely to be the cause of the failed nets.